1. Field of the Invention
The present invention relates in general to a method for the fabrication of a semiconductor device, and more particularly to a method of fabricating a semiconductor device using a damascene process.
2. Background of the Invention
Generally, semiconductor integration technologies using a damascene process are utilized more often in semiconductor devices that have high integration densities. For example, in a semiconductor fabrication process using a metal film as a gate electrode material, the use of a damascene process results in the formation of a gate electrode after a gate pattern and a source/drain region are formed. This can reduce the semiconductor substrate loss caused by thermal budgets and plasma. In addition, the use of a damascene process allows for the omission of a subsequent oxidation process and hence can prevent generation of the gate electrode defects caused by the oxidation process.
FIGS. 1A to 1E are cross-sectional views showing a method of forming a gate electrode using a damascene process according to the prior art.
First, as shown in FIG. 1A, a semiconductor device 1 includes a device isolation film. A dummy gate insulating film 2 and a dummy gate film 3 are deposited on top of the entire surface of device 1 in sequence. A photoresist pattern 4 is then formed on a gate electrode region of the dummy gate film 3.
Following its formation, the photoresist pattern is used as an etch barrier while the dummy gate film 3 and dummy gate insulating film 2 are sequentially etched. The etching forms a dummy gate electrode 5, as shown in FIG. 1B.
Next, ions such as low concentration n-type impurity ions, are implanted into the resulting substrate to form a lightly doped drain region LDD 6. Once the ions are implanted the photoresist pattern 4 is removed. Spacers 7 are then formed on both sidewalls of the dummy gate electrode 5 by a known manner. High concentration n-type impurity ions are subsequently implanted into a region intended for a source/drain region and then activated by a thermal process to form a source/drain region 8. Then, an interlayer insulating film 9 for insulating the respective devices is deposited on the resulting substrate.
Afterwards, as shown in FIG. 1C, the interlayer insulating film 9 is polished by Chemical Mechanical Polishing (CMP) in such a manner that the dummy gate electrode 5 is exposed. After polishing, the exposed dummy gate electrode 5 is removed by a dry etching process, thereby forming a groove 10 defining a region reserved for a gate electrode.
Next, as shown in FIG. 1D, a gate insulating film 11 is formed on the groove 10. The gate insulating film may be a grown thermal oxide film or a deposited high dielectric film. A doped polysilicon or metal film of a sufficient thickness is then deposited on top of the gate insulating film 11 to completely bury the groove 10.
The resulting substrate is then planarized by the CMP process in such a manner that the interlayer insulating film 9 is exposed. As a result, a gate electrode 12 is formed, as shown in FIG. 1E.
Although the conventional method of fabricating semiconductor devices using the damascene process allows gate electrodes to be formed, the method is not without its disadvantages. For instance, when forming the groove by etching the dummy gate electrode, the prior art carries out a dry etching process which results in loss of the semiconductor substrate and produces plasma process damage. Thus, if the resulting substrate having the groove is subjected to the gate electrode forming process as described above, the Gate Oxide Integrity (GOI) is significantly deteriorated.
In an attempt to solve such problems, a sacrificial oxide film is formed after removing the dummy gate electrode. This allows the elimination of the plasma process damage, but can further increase loss of the semiconductor substrate. As a result, the level of a channel region will be lower than the source/drain region. The low level channel region may cause the device to have a significant variance in its current driving force and voltage depending on a region.
Features of the present invention solve the above problems with the prior art by providing a unique method for fabricating a semiconductor device using a damascene process. The method can achieve a short channel effect even at a low threshold voltage and compensates for the substrate height loss caused by dry etching while eliminating plasma process damage caused by the dry etching.
It is another aspect of the present invention to provide a method for fabricating a semiconductor device using a damascene process, wherein the method can be carried out in a more stable manner and can improve the electrical properties of the device while enlarging a process margin to improve a yield of products.
The present invention provides a method for fabricating a semiconductor device using a damascene process, comprising the step of: depositing a dummy gate insulating film and a dummy gate electrode on a semiconductor substrate having a device isolation film; forming a source/drain region of a LDD structure in the semiconductor substrate; forming an interlayer insulating film on the resulting substrate; polishing and planarizing the interlayer insulating film by a Chemical Mechanical Polishing (CMP) until the dummy gate electrode is exposed; etching the dummy gate electrode using a dry etching process so as to expose the semiconductor substrate, thereby forming a groove; implanting impurity ions into the exposed portion of the substrate at a low ion implantation energy to form a delta-doping layer; heat-treating the resulting semiconductor substrate to diffuse the implanted impurity ions; growing a silicon film on the exposed portion of the substrate by a selective epitaxial process; depositing a gate insulating film on the surface of the groove; and depositing a gate metal film on the gate insulating film in the groove, thereby forming a gate electrode.